Key Takeaways
- Qualcomm and Amazon are deepening a multi‑generation partnership to ship custom AI‑inference silicon built for hyperscale data‑centers.
- The joint effort includes optical‑connectivity modules capable of 1.6 Tb/s, using Qualcomm’s latest SerDes and DSP technology.
- Qualcomm will run EDA workloads on AWS Bedrock, aiming to cut chip‑design cycles by up to 30 %.
- The collaboration targets lower power‑draw (≤ 5 W per TOPS), higher bandwidth, and reduced total‑cost‑of‑ownership (TCO) for AI workloads that are growing > 40 % YoY.
Overview of the Expanded Partnership
Custom AI‑Inference Silicon at Scale
Qualcomm Technologies, Inc. (QTI) and Amazon Web Services (AWS) have signed a multi‑generation agreement to co‑develop silicon that is purpose‑built for AI inference in large‑scale data‑centers. The chips will be fabricated on 7 nm/5 nm process nodes, delivering ≥ 15 TOPS/W while supporting the full breadth of AWS’s AI services (e.g., SageMaker, Bedrock).
High‑Performance Optical Connectivity (up to 1.6 Tb/s)
To match the exploding bandwidth needs of generative‑AI models, the partners are integrating optical I/O that can push 1.6 terabits per second across a single link. Qualcomm’s SerDes (serializer/deserializer) and optical DSP blocks will enable:
| Parameter | Qualcomm Solution | Typical Data‑Center Optical Link |
|---|---|---|
| Peak Data Rate | 1.6 Tb/s per lane | 400 Gb/s – 800 Gb/s per lane |
| Power per Gbps | ≤ 0.3 W/Gbps | 0.5 – 0.9 W/Gbps |
| Latency | < 150 ns | 200 – 300 ns |
| Integration | On‑chip SerDes + DSP | Separate transceiver modules |
The result is a 2‑3× reduction in energy per bit and a smaller footprint, critical for dense AI racks.
Leveraging AWS AI Services for Chip Design
Qualcomm will run its electronic‑design‑automation (EDA) workloads on AWS Bedrock, Amazon’s foundation model service. Early internal tests show design‑iteration times shrinking from 12 weeks to ~8 weeks, a ≈ 30 % acceleration that translates into faster time‑to‑market for custom ASICs.
Technical Highlights
| Feature | Specification | Benefit |
|---|---|---|
| Process Technology | 7 nm (2024) → 5 nm (2025) | Higher density, lower leakage |
| Inference Performance | ≥ 15 TOPS/W, 128 TOPS per die | Energy‑efficient scaling for LLMs |
| Optical Link | 1.6 Tb/s, 4× 400 Gb/s lanes | Supports multi‑model serving |
| Power Budget | ≤ 5 W per 100 TOPS | Cuts rack‑level power by ~20 % |
| Design Cycle | 8 weeks (via AWS Bedrock) vs 12 weeks | Faster silicon rollout |
These numbers align with the projected 40 % annual growth in AI compute demand across hyperscale clouds, according to IDC 2024 forecasts.
Industry Implications
- Data‑Center Operators: Lower OPEX through reduced power and cooling loads, while maintaining or expanding AI throughput.
- Chip Designers: Access to cloud‑native EDA tools shortens time‑to‑silicon, encouraging more niche, workload‑specific ASICs.
- AI Researchers: Faster inference latency and higher bandwidth enable real‑time generative‑AI services at scale.
Bottom Line
Qualcomm’s partnership with Amazon represents a strategic push to marry power‑efficient custom silicon with ultra‑high‑bandwidth optical interconnects, all while leveraging AWS’s AI‑cloud ecosystem to accelerate chip design. The combined offering promises significant energy savings, higher throughput, and a faster design loop, positioning both companies to meet the relentless growth of AI workloads in hyperscale environments.