Keysight expands interconnect testing with 16-channel system

Key Takeaways

• Double the channel density: 16 Tx + 16 Rx channels (2 × the FITS‑8CH offering).
• Supports 106 Gb/s and 212 Gb/s lane rates, enabling validation of 800 Gb/s and upcoming 1.6 Tb/s interconnects.
• Digital‑layer error analysis (BER + FEC) gives a system‑level view that pure physical‑layer testing cannot.
• Automated FIR‑tap tuning cuts lane‑setup time from days to a few minutes.
• Broad interconnect portfolio: full‑retimed optics, AOCs, LRO/LPO, active & passive copper, high‑speed fly‑over cables.

Overview of the FITS‑16CH System

Keysight Technologies has introduced the Functional Interconnect Test Solutions‑16CH (FITS‑16CH), a digital‑layer error‑performance validator that expands the company’s FITS family. The platform delivers 16 simultaneous transmit and 16 simultaneous receive paths, delivering twice the lane‑parallelism of the earlier FITS‑8CH instrument. Designed for R&D, product design, high‑volume manufacturing, and AI‑driven network deployments, FITS‑16CH targets the full‑assembly verification of optical, active‑copper, and passive‑copper interconnects.

Why Digital‑Layer Testing Is Critical

As data‑center link speeds climb past 100 Gb/s per lane, relying solely on physical‑layer metrics (e.g., insertion loss, jitter) no longer predicts real‑world error performance. FITS‑16CH combines bit‑error‑rate (BER) measurement with forward‑error‑correction (FEC) analysis at the digital layer, delivering a holistic view of how a complete cable or module behaves under production‑level traffic. This approach is essential for validating:

Supported Interconnect Families

FITS‑16CH is engineered to test a wide spectrum of link technologies, including:

The system’s generous insertion‑loss budget (up to 30 dB typical) accommodates lossy fixtures and long‑reach copper runs, ensuring accurate validation even in worst‑case scenarios.

Key Capabilities

1. Higher Channel Density for Full‑Assembly Validation

Two Module Compliance Boards (MCBs) operate independently, each handling eight Tx/Rx pairs. Teams can therefore evaluate up to 16 lanes in a single test cycle, dramatically increasing throughput for multi‑lane modules such as QSFP‑DD (8 × 100 Gb/s) or upcoming 16 × 100 Gb/s configurations.

2. Automated Lane Tuning

The FITS Windows 11 GUI integrates with Keysight’s DCA‑X platform to compute optimal finite‑impulse‑response (FIR) tap settings automatically. In practice, the tuning routine collapses from hours‑to‑days of manual iteration down to 3–5 minutes per lane, freeing engineering resources for higher‑value analysis.

3. Flexible Test Scenarios

Users can script BER sweeps, FEC‑threshold scans, and eye‑diagram captures across all 16 lanes simultaneously. Results are exported in CSV or JSON for downstream statistical processing.

FITS‑16CH vs. FITS‑8CH – Quick Comparison

Real‑World Applications

• Silicon‑chip validation: Verify silicon‑photonic transceivers before tape‑out.
• Network‑equipment qualification: Test QSFP‑DD and OSFP modules for carrier‑grade routers.
• Data‑center benchmarking: Provide operators with end‑to‑end error performance metrics for SLA reporting.
• High‑Performance Computing (HPC): Validate copper fly‑over cables that link compute nodes at 212 Gb/s per lane.