Keysight ADS unterstützt das PH18 Silizium-Photonik-PDK von Tower

Key Takeaways

• Keysight’s Advanced Design System (ADS) Photonic Designer now natively supports Tower Semiconductor’s PH18 silicon-photonic PDK.
• Designers can create, simulate, and layout photonic-integrated circuits (PICs) and co-design them with RF/electronic blocks in a single environment.
• The integrated flow eliminates costly data-hand-off, reduces model-translation errors, and speeds up verification for optical link rates ≥ 1.6 Tb/s.
• ADS delivers DRC-compliant layout, LVS checks, and physics-based component models, while final tape-out still uses Tower’s own verification suite.

Why a Unified Photonic-Electronic Design Flow Matters

Growing Bandwidth Demands

Modern data-center and telecom links are pushing 1600 Gb/s (1.6 Tb/s) and higher per wavelength. At these speeds, the interaction between electrical interconnects and optical waveguides becomes a dominant performance factor. Traditional design cycles split the work:

The split workflow forces engineers to export netlists, re-format S-parameters, and rebuild models, which adds weeks of effort and introduces error sources.

ADS + Tower PH18: One-Stop Shop

By embedding Tower’s PH18 PDK into ADS Photonic Designer, the same schematic can host:

• Electrical blocks (e.g., SiGe power amplifiers, RF front-ends)
• Photonic components (e.g., waveguides, grating couplers, modulators)

All elements share a common simulation kernel, enabling electrical-optical-electrical (EOE) co-simulation that predicts insertion loss, chirp, and bandwidth under realistic drive conditions.

Features Delivered by the Integrated Flow

Physics-Based Component Models

The PH18 PDK supplies parameterized models for:

These models are temperature-aware and can be linked directly into ADS’s RFPro EM solver for accurate electro-thermal analysis.

Layout Automation & Verification

• DRC-compliant photonic layout primitives generated from the PDK ensure that mask-level rules (minimum bend radius 5 µm, spacing ≥ 2 µm) are respected automatically.
• LVS (Layout-Versus-Schematic) checks verify that the physical implementation matches the intended circuit topology, catching mismatches before tape-out.

Seamless Transition to Foundry Tape-out

While ADS handles the design-to-verification loop, Tower’s own process-specific verification suite finalizes mask data preparation (MDP) and design-for-manufacturing (DFM) checks. This dual-tool approach preserves foundry compliance without sacrificing the integrated design experience.

Real-World Impact

• Design cycle reduction: Early reports from pilot teams show 30-40 % faster time-to-simulation compared with legacy multi-tool flows.
• Error mitigation: Co-simulation eliminates up to 90 % of model-translation discrepancies, as measured by post-tape-out performance drift.
• Scalability: The same workflow scales from single-channel transceivers to dense wavelength-division multiplexing (DWDM) modules with > 80 channels per chip.

Bottom Line

Keysight’s ADS Photonic Designer now fully supports Tower Semiconductor’s PH18 silicon-photonic PDK, delivering a single-environment workflow that bridges high-speed RF/electronic design with state-of-the-art photonic integration. Engineers can simulate, layout, and verify PICs alongside electronic circuits, cutting design time, reducing errors, and preparing chips for the 1.6 Tb/s optical links that will power next-generation data infrastructure. The solution is available immediately; further details are on keysight.com.