Cadence and ADI develop next-generation SHARC audio processors

Key Takeaways

• Cadence’s Tensilica DSP IP powers Analog Devices’ new ADSP‑SC84x/2184x SHARC‑FX family, delivering up to 5× the compute density of the prior ADSP‑SC59x/2159x line.
• Built on a 16 nm FinFET process (vs. 28 nm), the new silicon adds LPDDR4, extra L2 cache, a hardware‑security module (HSM) and optional connectivity cores for software‑defined vehicles.
• The SHARC‑FX core supports VLIW‑SIMD, mixed‑precision data types, and an expanded instruction set that can run real‑time neural‑network inference alongside classic DSP workloads.
• Target applications include seat‑level immersive audio, AI‑driven noise cancellation, voice assistants, and generative‑AI audio synthesis.
• Development is backed by Cadence’s compiler suite, ADI’s EZ‑KIT, CrossCore Embedded Studio, SigmaStudio+, and third‑party frameworks such as DSP Concepts’ Audio Weaver.

Introduction

Cadence’s Tensilica IP Group has teamed with Analog Devices, Inc. (ADI) to launch the next generation of SHARC automotive audio processors. By embedding Cadence’s VLIW‑SIMD DSP architecture into ADI’s forthcoming ADSP‑SC84x/2184x platform, the partnership aims to meet the rising compute, security, and connectivity demands of modern electric and autonomous vehicles.

Evolution from ADSP‑SC59x/2159x to ADSP‑SC84x/2184x

Why the shift matters

The move to a 16 nm node slashes switching energy by roughly 30 %, enabling higher clock rates (up to 1.2 GHz) while staying under the 1 W power budget typical for infotainment ECUs. The added LPDDR4 interface and larger L2 cache reduce memory stalls for AI kernels, a critical factor for real‑time noise‑cancellation and 3‑D audio rendering.

SHARC‑FX Core Architecture

The SHARC‑FX processor blends classic DSP strengths with AI flexibility:

• VLIW‑SIMD pipeline: Executes up to 8 parallel operations per cycle.
• Mixed‑precision support: 16‑bit, 32‑bit, and 8‑bit integer/floating‑point data types.
• Expanded ISA: Over 300 new instructions covering FIR/IIR filters, FFTs, matrix multiplies, and neural‑network primitives (e.g., MAC, ReLU, softmax).
• Hardware‑accelerated neural‑network kernels: Optimized for Google LiteRT, TensorFlow Lite Micro, and ONNX‑Runtime Lite, delivering up to 200 MMAC/s per core.

According to ADI, these capabilities allow real‑time edge inference for models up to 2 MB, enabling seat‑specific audio personalization and AI‑driven acoustic vehicle alerting systems (AVAS) without off‑board processing.

Application Portfolio

1. Automated‑Driving Alerts & AVAS – Precise tone shaping and adaptive volume control to meet regulatory standards.
2. Road‑Noise & Engine‑Order Cancellation (RNC/EOC) – Multi‑mic beamforming and adaptive filtering at > 48 kHz sample rates.
3. Personal Sound Zones (PSZ) & 3‑D Audio – Per‑seat binaural rendering with up to 64 virtual speakers.
4. Voice Assistants & Hands‑Free Comm – Low‑latency wake‑word detection (< 10 ms) and full‑duplex speech enhancement.
5. Generative‑AI Audio – On‑board synthesis of ambient soundscapes or alerts using lightweight diffusion models.

Development Ecosystem

• Cadence Tensilica Compiler & Debug Suite – Optimizes VLIW scheduling and SIMD utilization.
• ADI EZ‑KIT Evaluation Board – Rapid prototyping with plug‑and‑play audio I/O.
• CrossCore Embedded Studio (CCES) – Integrated IDE for firmware, DSP libraries, and performance profiling.
• SigmaStudio+ – Graphical signal‑flow design for rapid algorithm iteration.
• Audio Weaver (DSP Concepts) – High‑level block‑based modeling compatible with SHARC‑FX.

These tools streamline the transition from algorithmic research to production‑grade firmware, a critical path for OEMs racing to meet next‑gen vehicle launch windows.

Bottom Line

The Cadence‑ADI collaboration delivers a future‑proof SHARC audio processor that bridges traditional DSP workloads and emerging AI demands. With a 5× performance uplift, advanced security, and integrated connectivity, the ADSP‑SC84x/2184x platform positions itself as the cornerstone for in‑vehicle audio, voice, and safety systems in software‑defined, electrified vehicles. OEMs that adopt this solution can expect lower power consumption, faster time‑to‑market for AI features, and a secure, scalable