Cadence adds RTL generation to ChipStack AI Super Agent

Key Takeaways

• Cadence’s new RTL Generation Agent automates specification‑to‑RTL conversion, analysis, and refinement via natural‑language prompts.
• Early tests show 24 % average area savings and 18 % power reduction versus RTL produced only by a foundation model, with 100 % functional correctness.
• The agent works within Cadence’s hierarchical AI framework, allowing rapid updates to legacy RTL and early PPA feedback.
• Honda R&D is the first major customer evaluating the technology for safety‑critical automotive SoCs.
• General availability for select early‑access users is slated for Q4 2026 as part of the expanded ChipStack and InnoStack AI Super Agent portfolios.

Cadence Extends ChipStack AI Super Agent to RTL Generation

Cadence Design Systems has unveiled an RTL Generation Agent that plugs into its existing ChipStack AI Super Agent platform. The new module shifts the AI‑driven workflow from pure verification and debugging to the front‑end creation and optimisation of RTL. Engineers supply high‑level, natural‑language specifications—such as target power, performance, and area (PPA) metrics—and the agent produces synthesizable Verilog/VHDL code, performs preliminary PPA analysis, and iteratively refines the design until the goals are met.

How the Agent Operates

Cadence’s AI architecture relies on a tiered system of “super agents” that orchestrate specialised task agents. In this hierarchy:

The RTL Generation Agent integrates Cadence’s commercial EDA tools (e.g., Genus™ Synthesis, Innovus™ Implementation) into its workflow, ensuring that generated code is immediately compatible with downstream place‑and‑route and sign‑off flows.

Quantitative Results from Early Evaluations

Cadence reports that, across a benchmark suite of 12 digital blocks (ranging from 2 k to 30 k gates), the RTL Generation Agent delivered average area reductions of 24 % and average power reductions of 18 % when compared with RTL generated solely by a generic foundation model. Functional verification showed 100 % coverage of intended behaviour after the first refinement pass.

These figures illustrate that AI‑guided optimisation can deliver tangible silicon‑level benefits without sacrificing correctness.

Real‑World Validation: Honda R&D Pilot

Honda’s automotive R&D division has begun a pilot program using the RTL Generation Agent on system‑on‑chip (SoC) blocks for advanced driver‑assistance systems (ADAS). The automotive market imposes stringent safety standards (ISO 26262 ASIL‑D) and tight power envelopes (< 150 mW per core). Early feedback indicates that the agent can incorporate safety‑critical constraints directly into the RTL, reducing manual safety‑analysis effort by an estimated 40 %.

Updating Legacy RTL and Early PPA Feedback

A common pain point in chip design is the revision of legacy RTL when product requirements shift. The new agent accepts high‑level change requests—such as “increase clock frequency to 1.2 GHz” or “lower core leakage by 15 %”—and automatically rewrites the affected RTL sections. It then runs a quick PPA estimate, delivering designers a first‑order impact report within minutes, compared to the typical days‑long manual re‑synthesis cycle.

Strategic Fit Within Cadence’s “Design for AI, AI for Design” Roadmap

The RTL Generation Agent broadens Cadence’s AI Super Agent ecosystem, which already includes:

• InnoStack AI Super Agent – AI‑enhanced flows for analog and mixed‑signal design.
• ViraStack AI Super Agent – AI‑driven verification across digital, analog, and software domains.

Together, these portfolios embody Cadence’s dual‑track strategy: applying AI to accelerate chip creation while building hardware and software platforms optimized for AI workloads.

Availability Timeline

Cadence plans to ship the expanded ChipStack and InnoStack capabilities to a hand‑picked group of early‑access customers in Q4 2026. General availability is expected in early 2027, subject to feedback from pilot programs such as Honda’s.

Bottom Line

Cadence’s RTL Generation Agent marks a decisive step toward fully AI‑orchestrated front‑end design. By delivering measurable area and power gains, guaranteeing functional correctness, and enabling rapid RTL updates, the technology promises to shorten design cycles and lower development costs—especially for safety‑critical automotive SoCs. With early‑access roll‑out slated for late 2026, the industry can expect a new benchmark for AI‑driven RTL creation within the next year.