Automation

Siemens expands agentic AI for 3D IC design workflows

Siemens expands agentic AI for 3D IC design workflows

Key Takeaways

  • Siemens and NVIDIA have merged agentic AI with accelerated computing to streamline 3D‑IC electro‑thermal design.
  • The new workflow cuts engineering effort by up to 95 %, reduces workflow‑setup time by up to 99 %, and expands design‑space coverage ≈ 50× versus traditional manual methods.
  • NVIDIA’s Rubin GPU delivers 50 PFLOPS of FP16 inference and up to 288 GB of HBM4 memory, creating a high‑density thermal challenge that must be addressed early in the design cycle.
  • The AI‑driven process orchestrates nine steps across seven Siemens tools, performing 50‑100 reasoning cycles in an 8‑10‑minute run.

Siemens‑NVIDIA Agentic AI Boosts 3D‑IC Design

Siemens announced a major upgrade to its electronic design automation (EDA) portfolio, built in partnership with NVIDIA. The enhancement layers the agentic AI concepts unveiled at DAC 2026 on top of NVIDIA’s GPU‑accelerated hardware, delivering an end‑to‑end solution for electrical, power, thermal, and co‑design analysis of three‑dimensional integrated circuits.

Unified Electro‑Thermal Workflow

Using Siemens’ Design Space Exploration and Optimization (DSE/DSO) framework, the new workflow automatically links the company’s electro‑thermal solvers into a single, physics‑based sign‑off loop. Benchmark data supplied by Siemens shows:

Metric Manual Workflow Agentic AI Workflow
Engineering effort 100 % (baseline) ≤ 5 % (‑95 %)
Setup time 1 h per iteration ≤ 0.01 h (‑99 %)
Design‑space coverage Limited to few hundred variants ≈ 50× more variants
Reasoning steps per run Manual, ad‑hoc 50‑100 automated
Total run time 30‑60 min per variant 8‑10 min for full cycle

The table underscores how the AI agent eliminates repetitive data transfers and manual bookkeeping, letting engineers focus on high‑level objectives.

Packaging Pressures for AI‑Enabled Systems

AI accelerators demand massive compute density, which translates into heightened thermal loads. NVIDIA’s Rubin GPU—the core of the Vera Rubin NVL72 system—offers:

  • 50 PFLOPS of FP16 inference performance (NVFP4).
  • 288 GB of HBM4 memory bandwidth per GPU.

When multiple Rubins are stacked, power density can exceed 1 kW/cm², making heat removal a primary design constraint. Consequently, electro‑thermal co‑design must be embedded early rather than deferred to final verification.

Why Manual Coordination Falls Short

Traditional 3D‑IC flows require specialists in separate domains (electrical, power, thermal, extraction) to shuttle data between nine or more tools. As chip complexity rises, teams often prune the number of explored scenarios to meet schedule and compute limits, delaying detection of power‑delivery or hot‑spot issues until late in the tape‑out stage.

How the Agentic Workflow Operates

  1. Objective definition – The designer inputs performance, power, and thermal targets into Fuse EDA AI Agent (hosted in Intelligence Center X).
  2. Tool orchestration – The agent triggers seven Siemens EDA modules, executing coupled electro‑thermal simulations.
  3. Root‑cause analysis – If any target is missed, the AI pinpoints whether the culprit lies in power delivery network, component placement, material selection, or a combination thereof.
  4. Design‑space steering – Using the analysis outcomes, the agent iteratively explores alternative layouts, material stacks, and cooling strategies, automatically rerunning the physics solvers.
  5. Result synthesis – After 50‑100 reasoning loops, the system presents a ranked list of configurations that satisfy the original objectives, often revealing solutions that would be missed in a manual scan.

The entire loop completes in 8‑10 minutes, delivering a breadth of design alternatives that would otherwise require days of engineer time.

Bottom Line

By fusing agentic AI with NVIDIA’s high‑performance GPUs, Siemens delivers a dramatically faster, more thorough 3D‑IC design flow. Engineers can now evaluate dozens of electro‑thermal scenarios in minutes, cutting effort by up to 95 % and uncovering power‑thermal risks far earlier than legacy methods permit. For chipmakers racing to integrate AI accelerators into compact packages, this capability represents a decisive productivity and risk‑mitigation advantage.

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