Siemens and TSMC expand AI and 3D IC design enablement

Key Takeaways

• Siemens and TSMC deepen their partnership inside the TSMC Open Innovation Platform (OIP) to accelerate AI‑driven semiconductor design.
• An AI‑powered agent now automates Design Rule Check (DRC) fixing across both digital and custom IC flows, cutting manual effort by ≈70 % and shortening tape‑out timelines.
• The Fuse EDA AI System and Fuse AI Agent, powered by NVIDIA tensor cores, enable autonomous, self‑verifying EDA workflows that coordinate multiple tools in real time.
• Multi‑machine support in Calibre 3DStack Advanced brings chip‑on‑wafer‑on‑substrate (CoWoS‑L) and TSMC‑SoIC verification into a single, unified environment.
• The combined solution targets the growing complexity of 3‑D ICs, promising up to 30 % faster design convergence for 3DFabric technologies.

Siemens‑TSMC Collaboration Overview

Siemens and Taiwan Semiconductor Manufacturing Company (TSMC) have announced an expanded joint effort within the TSMC Open Innovation Platform (OIP). The goal is to embed artificial‑intelligence (AI) throughout the semiconductor design lifecycle, from early schematic capture to final tape‑out. By integrating Siemens’ Calibre, Aprisa, and Solido Fuse toolsets with TSMC’s process libraries, the partnership aims to:

• Boost productivity on complex multi‑chiplet projects.
• Reduce design‑cycle times that typically range from 12–18 months for advanced nodes to 8–10 months with AI assistance.
• Manage the escalating rule density of 5‑nm and finer geometries (often > 10 M design rules per chip).

AI‑Enabled DRC Fix Workflow

How the Agent Works

The AI agent parses Calibre DRC reports, automatically classifies violations, and generates corrective layout edits. It then validates the changes in‑situ using Calibre Check Assist, which supplies contextual rule information to guide the AI’s decision‑making. The loop repeats until the design meets the target rule set, allowing engineers to focus on higher‑level architectural tasks.

Technical Highlights

• NVIDIA TensorRT integration reduces token consumption by ≈ 45 %, enabling longer reasoning chains across complex design hierarchies.
• The Fuse AI Agent can orchestrate up to 12 EDA tools simultaneously, handling placement, routing, and timing analysis in a single autonomous workflow.
• Early trials on a 5‑nm digital macro reported a 30 % reduction in total design‑iteration count (from 10 to 7 cycles).

Extending AI to 3‑D IC Design

3DFabric Enablement

Siemens has upgraded Calibre 3DStack Advanced to support multi‑machine verification of inter‑chiplet antenna structures and wafer‑level stacking. Key capabilities include:

• TSMC‑SoIC (System‑on‑Integrated‑Chip) support for ≤ 2 µm interconnect pitch and ≤ 10 µm die‑to‑die alignment tolerances.
• Ongoing certification for CoWoS‑L (Chip‑on‑Wafer‑on‑Substrate) with local silicon interconnects, targeting ≥ 200 GB/s I/O bandwidth per stack.

These enhancements allow designers to run full‑stack electromagnetic and mechanical checks across up to 64 stacked dies in a single job, a task that previously required separate, time‑consuming manual analyses.

AI‑Driven Place‑and‑Route for Chiplets

Aprisa’s AI engine now provides domain‑specific guidance for chiplet placement, automatically balancing thermal, power, and signal‑integrity constraints. In benchmark runs on a 7‑nm 3‑D ASIC:

• Placement runtime dropped from 4.5 h to 1.8 h.
• Routing congestion was reduced by ≈ 25 %, improving post‑routing timing closure rates.

Bottom Line

The Siemens‑TSMC alliance is delivering a concrete, AI‑centric toolbox that tackles the twin challenges of rule‑heavy design verification and the rising complexity of 3‑D IC stacking. By automating DRC fixes, orchestrating multi‑tool EDA flows, and extending verification to advanced 3DFabric platforms, the partnership promises significant cycle‑time reductions (up to 30 %) and higher first‑pass yield for next‑generation silicon. For chipmakers racing to adopt