Cadence expands TSMC collaboration for AI chip design

Key Takeaways

• Cadence expands collaboration with TSMC to accelerate AI-driven semiconductor innovation
• The partnership delivers IP, signoff-ready design infrastructure, and certified flows for leading-edge AI silicon on TSMC's N3, N2, A16, and A14 process technologies
• Cadence provides a rich IP portfolio, including DDR5 12.8G MRDIMM, PCIe 6.0, and HBM4E 16G, for TSMC N2P
• The company enables certified, end-to-end EDA flows for advanced-node SoCs, chiplet, and 3D-IC designs

Introduction to Cadence and TSMC Collaboration

Cadence has announced an expansion of its long-standing relationship with TSMC to accelerate AI-driven semiconductor innovation. This collaboration aims to deliver IP, signoff-ready design infrastructure, and certified flows for leading-edge AI silicon on TSMC's N3, N2, A16, and A14 process technologies. The partnership will help customers reduce iterations and improve correlation for DTCO-focused advanced AI and HPC designs, accelerating time to silicon with greater confidence.

Design for AI: Silicon-Proven IP and Certified Flows

Cadence is delivering a rich IP portfolio for TSMC N2P, including:

AI for Design: Agent-Ready Infrastructure

Cadence's agentic AI boosts productivity in AI semiconductor and 3D-IC design by shifting EDA from tool-by-tool workflows to goal-driven, agentic execution. The company is preparing "agent-ready" design flows, optimization engines, and signoff infrastructure in collaboration with TSMC. These capabilities enable AI systems to combine domain reasoning with physics-based analysis, driving convergence of PPA and reliability tradeoffs across all aspects.

Bottom Line

In summary, the expanded collaboration between Cadence and TSMC is set to accelerate AI-driven semiconductor innovation, delivering IP, signoff-ready design infrastructure, and certified flows for leading-edge AI silicon. With a rich IP portfolio and certified, end-to-end EDA flows, Cadence is poised to help customers reduce iterations and improve correlation for DTCO-focused advanced AI and HPC designs. The partnership's focus on "agent-ready" infrastructure will also enable AI systems to drive convergence of PPA and reliability tradeoffs, further accelerating time to silicon with greater confidence.