QuickLogic expands eFPGA Hard IP for GF 12LP

Key Takeaways

• QuickLogic’s upgraded eFPGA Hard IP for GlobalFoundries 12‑LP (GF 12LP) adds a dedicated DSP MAC engine with SIMD and cascade support.
• The fabric now scales past 250 k LUTs, enabling far larger on‑chip programmable blocks.
• An optional Configuration‑Bit Health Monitor provides real‑time SEU detection and correction for mission‑critical reliability.
• Full RTL‑to‑bitstream flow is supported through QuickLogic’s Aurora and Aurora PRO toolchains.

Overview of the Expanded eFPGA Hard IP

QuickLogic has leveraged its silicon‑proven eFPGA architecture to deliver a next‑generation Hard IP block that can be embedded directly into a System‑on‑Chip (SoC) fabricated on GlobalFoundries’ 12‑level‑planar (12‑LP) process. The new IP targets compute‑intensive workloads—such as phased‑array radar, electronic warfare, 5G/6G wireless infrastructure, satellite communications, and high‑resolution imaging—while also meeting the stringent reliability demands of aerospace and defense systems.

New DSP Multiply‑and‑Accumulate (MAC) Unit

• Architecture: Single‑instruction‑multiple‑data (SIMD) MAC with a pre‑adder stage and cascade routing.
• Performance: Up to 2 × 10⁹ MAC operations per second at 1 GHz core frequency (typical for GF 12LP).
• Application Fit: Enables real‑time beam‑forming, FIR filtering, and matrix‑vector multiplication with lower latency than external DSP blocks.

Scalability Beyond 250 k LUTs

• Maximum LUT Count: > 250 000 lookup tables (LUTs) per eFPGA instance, a 40 % increase over the previous 180 k‑LUT limit.
• Block RAM: Up to 1 MB of embedded BlockRAM can be provisioned alongside the LUT fabric.
• Design Flexibility: Users can mix‑and‑match LUT, BRAM, and DSP resources to tailor the fabric to specific algorithmic footprints.

Optional Configuration‑Bit Health Monitor

• Function: Continuously scrubs configuration memory for Single‑Event Upsets (SEUs) and automatically rewrites corrupted bits while the user design remains active.
• Detection Latency: < 5 µs from upset to correction, ensuring near‑real‑time integrity.
• Reliability Impact: Improves Mean Time Between Failures (MTBF) by an estimated 10× for radiation‑prone environments.

Development Ecosystem

QuickLogic supplies end‑to‑end tooling:

The toolset produces a complete RTL‑to‑bitstream path, allowing designers to iterate rapidly and embed updates post‑fabrication—critical for long‑life products.

Feature Comparison: Legacy vs. Expanded eFPGA (GF 12LP)

Bottom Line

QuickLogic’s expanded eFPGA Hard IP for GF 12LP delivers a compelling blend of compute density, scalability, and reliability. By integrating a SIMD‑capable DSP MAC, supporting over 250 k LUTs, and offering an on‑the‑fly configuration‑bit health monitor, the IP positions itself as a go‑to solution for next‑generation radar, wireless, and space‑borne systems that demand both performance and fault tolerance. Coupled with the Aurora/Aurora PRO development suite, designers can accelerate time‑to‑market while retaining the flexibility to update hardware post‑production.

For detailed specifications and licensing information, visit quicklogic.com.