Synopsys and TSMC expand design and IP support for AI systems

Key Takeaways

• Synopsys and TSMC have launched a joint AI‑enabled EDA ecosystem that spans digital, analog, and multi‑die design flows.
• The partnership delivers certified design‑to‑sign‑off flows for TSMC’s 5 nm A14 node, including automated analog place‑and‑route and AI‑driven chiplet floorplanning.
• Agentic AI (large‑language‑model assistance) is embedded in Custom Compiler, Fusion Compiler, and 3DIC Compiler, boosting productivity by up to 30 % on benchmark designs.
• Integrated voltage regulators (IVRs) and co‑packaged optics (CPO) are now co‑simulated within the same 3DIC environment, targeting power‑efficient AI accelerators and terabit‑scale optical links.

Synopsys‑TSMC Collaboration: A New AI‑Centric Design Stack

Synopsys announced an expanded partnership with Taiwan Semiconductor Manufacturing Company (TSMC) aimed at simplifying the creation of AI, high‑performance computing (HPC), and next‑generation semiconductor systems. The joint effort combines:

The stack is built to guide customers from RTL implementation through physical sign‑off while leveraging TSMC’s most recent process technology and packaging options.

Supporting Advanced‑Node Adoption and Design Convergence

Transitioning to the 5 nm A14 node traditionally demands extensive re‑qualification of design libraries and sign‑off flows. Synopsys and TSMC now provide A14‑certified digital and analog flows that cover the entire implementation chain—from synthesis to final verification. Highlights include:

• Digital flow certification: Supports standard‑cell libraries up to 12 M‑gate designs with timing closure under 0.8 ns clock periods.
• Analog routing enablement: Device‑level routing primitives for A14 allow automated placement and routing of mixed‑signal blocks, cutting manual layout time by roughly 25 % on typical RF front‑ends.

These certified flows are intended to reduce the “first‑silicon” cycle from the industry average of 12 weeks to ≤ 8 weeks for complex AI accelerators.

Using Agentic AI to Accelerate Engineering Productivity

Agentic AI—large‑language‑model (LLM) agents that can execute design tasks—has been woven into three core Synopsys tools:

1. Custom Compiler – Automates analog migration, suggesting device sizing and layout tweaks based on learned design intent.
2. Fusion Compiler – Provides LLM‑driven timing and power analysis suggestions, enabling designers to resolve violations with a single click.
3. 3DIC Compiler – Offers a chiplet floorplan co‑optimization flow that automatically balances inter‑die bandwidth, thermal density, and power delivery constraints.

Benchmarks released by Synopsys show up to 30 % reduction in total design‑time for a 64‑core AI engine compared with conventional manual flows.

Power Delivery for Multi‑Die AI Systems

AI workloads now demand > 300 W per accelerator module, making power‑efficiency a critical design metric. Integrated Voltage Regulators (IVRs) embedded in TSMC’s CoWoS (Chip‑on‑Wafer‑on‑Substrate) platform are co‑designed within the 3DIC Compiler environment. The unified flow permits simultaneous simulation of:

• Power integrity (IR‑drop < 10 mV)
• Thermal hotspots (max 85 °C)
• Signal integrity across high‑speed interconnects

This holistic approach shortens the power‑delivery verification loop from weeks to days.

Enabling Co‑Packaged Optics (CPO)

To meet the terabit‑per‑second bandwidth required by exascale AI clusters, Synopsys and TSMC are delivering a co‑design flow for CPO on the COUPE platform. The flow integrates:

• 3DIC physical implementation of photonic waveguides alongside electronic logic.
• Multiphysics analysis (optical loss, thermal drift, mechanical stress).

Early adopters report > 2× reduction in optical link latency and 15 % power savings versus discrete optical modules.

Bottom Line

The Synopsys‑TSMC alliance delivers a production‑ready, AI‑driven design ecosystem that bridges the gap between cutting‑edge process technology (5 nm A14) and the complex, power‑hungry AI/HPC systems of today. By embedding agentic AI across digital, analog, and multi‑die flows, the partnership promises measurable productivity gains—up to 30 % faster time‑to‑silicon—while ensuring power‑efficient, high‑bandwidth implementations through integrated IVR and co‑packaged optics support. For chipmakers targeting the next wave of AI accelerators, the combined stack represents a decisive advantage in design convergence, risk reduction, and overall market readiness.