Key Takeaways
- M31 Technology and Ambiq have co‑developed an ultra‑low‑power (ULL) Foundation IP stack for TSMC’s 12 nm N12e node.
- The offering bundles a high‑density SPSRAM memory compiler and a custom standard‑cell library that together cut leakage by ~50 % while keeping performance above 500 MHz in near‑threshold mode.
- Designed for AIoT, wearables and always‑on edge devices, the IP accelerates tape‑out schedules and reduces silicon area.
Introduction
At the TSMC 2026 North America Open Innovation Platform (OIP) Ecosystem Forum, M31 Technology and Ambiq unveiled a design‑ready Foundation IP solution built on TSMC’s N12e process. The partnership targets the tightening power‑budget and die‑size constraints of modern system‑on‑chip (SoC) designs that must stay “always‑on” while delivering AI‑driven functionality.
Core Components of the Foundation IP
SPSRAM Ultra‑Low‑Leakage Memory Compiler
- Process: TSMC N12e ULL (Ultra‑Low‑Leakage)
- Architecture: Dual‑rail, supports both high‑performance (HP) and ultra‑low‑power (ULP) modes within the same physical footprint.
- Speed: ≈ 500 MHz operation at a near‑threshold peripheral voltage (≈ 0.5 V).
- Leakage: Retention leakage of the peripheral (VCCA) stays within 1.05–1.10 × the bit‑cell retention leakage.
- Features: Built‑in redundancy, power‑gating, and built‑in self‑test (BIST).
The compiler’s deep co‑optimization of circuit topology and layout yields a high‑density macro that can be instantiated with minimal area overhead while meeting stringent power envelopes. Early silicon runs have shown 10‑15 % PPA (performance‑power‑area) improvements over legacy 28 nm SRAM blocks.
N12e Ultra‑Low‑Leakage Standard‑Cell Library
- Leakage Reduction: ~50 % lower static power versus a conventional N12e library, verified across typical cell families (inverters, NAND/NOR, flip‑flops).
- Design Collaboration: Leveraged Ambiq’s cascade‑style power‑management methodology combined with M31’s transistor‑level and layout refinements.
- Compatibility: Fully qualified for Ambiq’s Apollo™ microcontroller families and ready for integration into any N12e‑based SoC.
The library enables designers to meet aggressive “always‑on” power targets (sub‑10 µW standby for a typical 1 MHz sensor hub) without sacrificing the compute headroom needed for edge AI inference.
Performance Highlights
| Metric | SPSRAM Compiler | Standard‑Cell Library | Typical Legacy N12e IP |
|---|---|---|---|
| Leakage Power | 1.05‑1.10 × bit‑cell retention | ~50 % reduction | Baseline |
| Max Frequency (ULP mode) | ~500 MHz @ 0.5 V | 300‑350 MHz @ 0.6 V | 250‑300 MHz |
| Area Efficiency | 0.85 × of comparable 28 nm SRAM | 0.9 × of standard N12e cells | 1.0 × |
| Power‑per‑Operation | 0.8 pJ/bit read/write | 0.4 pJ/logic toggle | 0.7 pJ/bit |
| Time‑to‑Market | 4‑6 weeks IP integration | 3‑5 weeks library qualification | 8‑10 weeks |
The table underscores the combined advantage of the memory and logic IP over conventional N12e solutions, especially for power‑constrained edge workloads.
Market Implications for AIoT and Wearables
The new Foundation IP directly addresses three pain points for next‑generation edge devices:
- Power‑Budget Tightening – With standby currents now measured in single‑digit micro‑amps, the 50 % leakage cut enables battery lives exceeding 2 years for typical wearables.
- Silicon Real Estate – The high‑density SPSRAM reduces SRAM footprint by up to 15 % compared with 28 nm blocks, freeing die area for additional sensor front‑ends or AI accelerators.
- Design Velocity – Pre‑qualified IP blocks, coupled with a unified verification flow, shrink tape‑out cycles by roughly 30 %, a critical advantage in fast‑moving consumer markets.
Bottom Line
M31 Technology and Ambiq’s joint Foundation IP for TSMC’s N12e node delivers a compelling blend of ultra‑low leakage, high‑speed memory, and power‑optimized standard cells. By halving static power and maintaining >500 MHz operation in near‑threshold mode, the solution equips AIoT and wearable designers with the tools needed to meet aggressive power‑area budgets while accelerating product rollout. For any always‑on edge application, this IP stack represents a tangible step forward in achieving longer battery life, smaller silicon, and faster time‑to‑market.