Cadence, AI ve HPC tasarımı için TSMC ortaklığını genişletiyor

Key Takeaways

• Cadence’in tasarım-araç paketi artık TSMC’nin A14, A16, N2P, N3 ve N3P süreç düğümleri için sertifikalıdır.
• Innovus-tabanlı dijital akış ve Virtuoso-tabanlı analog akış, AI/HPC SoC’ları için yineleme süresini 2.5×'ye kadar azaltıyor.
• Yeni silikon-doğrulanmış IP blokları (UCIe-64G, LPDDR6, DDR5, PCIe 6.0) zaten A14/N2P üzerinde taslak çıkartıldı ve Q4 2026'da gönderilecek.
• Cadence, yüzlerce chiplet ve milyonlarca mikro-bumper entegrasyonu yapabilen wafer-scale sistemler için TSMC 3DFabric'i destekliyor.

Cadence Extends Its Alliance with TSMC

Cadence Design Systems ve Taiwan Semiconductor Manufacturing Company (TSMC), AI ve yüksek performanslı bilgi işlem (HPC) çip yaratımını hızlandırmak için iş birliğini derinleştirdi. Ortak çaba artık TSMC’nin en gelişmiş mantık ve ileri paketleme platformlarını—A14, A16, N2P, N3 ve N3P—kapsıyor ve agentic-AI ve 3-D-IC mimarileri için sorunsuz bir “tasarım-dan-silikona” yolu sağlıyor.

Certified Tool Flows for A14 & A16

The digital suite also integrates Pegasus Verification, Liberate Characterization, and Genus Synthesis, delivering a complete end-to-end environment for AI-centric SoCs.

New Silicon-Proven IP

• UCIe-64G (Universal Chiplet Interconnect Express) taped out on A14, now in silicon validation on N3P.
• LPDDR6 memory IP in active development; expected silicon release Q4 2026.
• Artisan Foundation IP (standard cells, GPIO, memory compilers) targeting AI/HPC and networking workloads, slated for Q4 2026.

These blocks are pre-qualified for TSMC’s 3DFabric ecosystem, allowing designers to stitch together heterogeneous chiplets with hundreds of interconnects and millions of micro-bumps.

N2P Flow Certification – Targeting Infrastructure & Physical AI

Cadence’s analog, digital, and sign-off flows have earned certification on TSMC’s N2P (7 nm) node, a platform optimized for power-efficient AI inference and edge-infrastructure chips.

• Virtuoso Layout Suite now includes enhanced connectivity models, shortening the time-to-first-layout.
• Taped-out IP on N2P includes DDR5, LPDDR5, and PCIe 6.0; PCIe 3.0 is scheduled for Q4 2026.
• UCIe-64G silicon on N2P is currently in the TSMC testing lab and has already been characterized on the N3P node.

These certifications promise faster tape-outs and higher productivity for designers tackling data-center AI accelerators and physical-AI sensor processors.

Scaling to Hundreds of Chiplets with 3DFabric & COUPE

Cadence’s portfolio now fully supports TSMC’s SoW-X (System-on-Wafer-X) 3DFabric flow, enabling:

• Integration of >100 chiplets within a single wafer-scale package.
• Millions of micro-bump interconnects, facilitating high-bandwidth, low-latency communication between compute, memory, and I/O domains.
• Compatibility with TSMC-COUPE (Chiplet-On-Package-Enabled) design rules, ensuring manufacturability at advanced nodes.

This capability is critical for next-generation AI processors that rely on modular chiplet architectures to overcome the physical limits of monolithic dies.

Bottom Line

Cadence’s expanded partnership with TSMC delivers a fully certified, end-to-end design environment across the company’s most advanced process technologies—from A14/A16 logic to N2P/N3P advanced packaging. By bundling AI-focused IP, accelerated design flows, and 3DFabric support, the alliance equips silicon architects with the tools needed to bring agentic-AI and HPC chiplets to market faster, with fewer design iterations and higher first-pass yield. For companies targeting wafer-scale AI engines or high-density HPC accelerators, Cadence-TSMC’s joint offering now represents the most comprehensive, production-ready pathway available.