Cadence erweitert TSMC-Partnerschaft für KI- und HPC-Design

Key Takeaways

• Cadence’s design-tool suite is now certified for TSMC’s A14, A16, N2P, N3, and N3P process nodes.
• The Innovus-based digital flow and Virtuoso-based analog flow cut iteration time by up to 2.5× for AI/HPC SoCs.
• New silicon-proven IP blocks (UCIe-64G, LPDDR6, DDR5, PCIe 6.0) are already taped-out on A14/N2P and will ship Q4 2026.
• Cadence supports TSMC 3DFabric for wafer-scale systems that can integrate hundreds of chiplets and millions of micro-bumps.

Cadence Extends Its Alliance with TSMC

Cadence Design Systems and Taiwan Semiconductor Manufacturing Company (TSMC) have deepened their collaboration to accelerate AI and high-performance computing (HPC) chip creation. The joint effort now spans TSMC’s most advanced logic and advanced packaging platforms—A14, A16, N2P, N3, and N3P—enabling a seamless “design-to-silicon” path for agentic-AI and 3-D-IC architectures.

Certified Tool Flows for A14 & A16

The digital suite also integrates Pegasus Verification, Liberate Characterization, and Genus Synthesis, delivering a complete end-to-end environment for AI-centric SoCs.

New Silicon-Proven IP

• UCIe-64G (Universal Chiplet Interconnect Express) taped out on A14, now in silicon validation on N3P.
• LPDDR6 memory IP in active development; expected silicon release Q4 2026.
• Artisan Foundation IP (standard cells, GPIO, memory compilers) targeting AI/HPC and networking workloads, slated for Q4 2026.

These blocks are pre-qualified for TSMC’s 3DFabric ecosystem, allowing designers to stitch together heterogeneous chiplets with hundreds of interconnects and millions of micro-bumps.

N2P Flow Certification – Targeting Infrastructure & Physical AI

Cadence’s analog, digital, and sign-off flows have earned certification on TSMC’s N2P (7 nm) node, a platform optimized for power-efficient AI inference and edge-infrastructure chips.

• Virtuoso Layout Suite now includes enhanced connectivity models, shortening the time-to-first-layout.
• Taped-out IP on N2P includes DDR5, LPDDR5, and PCIe 6.0; PCIe 3.0 is scheduled for Q4 2026.
• UCIe-64G silicon on N2P is currently in the TSMC testing lab and has already been characterized on the N3P node.

These certifications promise faster tape-outs and higher productivity for designers tackling data-center AI accelerators and physical-AI sensor processors.

Scaling to Hundreds of Chiplets with 3DFabric & COUPE

Cadence’s portfolio now fully supports TSMC’s SoW-X (System-on-Wafer-X) 3DFabric flow, enabling:

• Integration of >100 chiplets within a single wafer-scale package.
• Millions of micro-bump interconnects, facilitating high-bandwidth, low-latency communication between compute, memory, and I/O domains.
• Compatibility with TSMC-COUPE (Chiplet-On-Package-Enabled) design rules, ensuring manufacturability at advanced nodes.

This capability is critical for next-generation AI processors that rely on modular chiplet architectures to overcome the physical limits of monolithic dies.

Bottom Line

Cadence’s expanded partnership with TSMC delivers a fully certified, end-to-end design environment across the company’s most advanced process technologies—from A14/A16 logic to N2P/N3P advanced packaging. By bundling AI-focused IP, accelerated design flows, and 3DFabric support, the alliance equips silicon architects with the tools needed to bring agentic-AI and HPC chiplets to market faster, with fewer design iterations and higher first-pass yield. For companies targeting wafer-scale AI engines or high-density HPC accelerators, Cadence-TSMC’s joint offering now represents the most comprehensive, production-ready pathway available.